1. Technical Field
In general, embodiments of the present invention relate to hard mask removal. Specifically, embodiments of the present invention relate to dielectric hard mask removal during the FinFET formation process.
2. Related Art
As semiconductor device scaling continues, the ability to control leakage currents and otherwise develop improved devices becomes more difficult. MOSFET technologies (e.g., FinFET devices), have been developed to overcome such limitations to transistor scaling. While thinner body FinFET devices can be used to obtain more aggressive gate length scaling to suppress short-channel effects, and to increase the effective channel width by combining multiple fins, the ability to fabricate fin structures with tight or narrow pitches was conventionally limited by capabilities of standard photolithography technologies. Along similar lines, FinFET devices may experience uniformity issues and/or damage caused by etching processes utilized to remove hard mask layers during device formation. Specifically, under existing approaches, wet/dry etching processes are performed so that hard mask layers may be removed. Unfortunately, such processes often cause damage to fin surfaces resulting in a lack of uniformity (e.g., an uneven fin profile).